Melay machine finite state machine design in vhdl
This tutorial is about implementing a finite state machine is vhdl. I will go through each and every step of designing a finite state machine and simulating it. Xilinx is used as a tool to construct finite state machine and for simulation and testing purpose. I suppose you know what is finite state machine and why it is used? I will give a short introduction of finite state machines and then move on to the designing phase.

So what is finite state machine?Finite state machine is a graphical model/representation of sequential activities or events. After representing and modeling the events they can be implemented easily in case of sequential logic designs.
Finite state machines can be utilized in many fields of study e.g neural networks, artificial intelligence, mathematics, games, robotics and sequential flow of data. Since we are dealing with the sequential circuits so i will explain their use in sequential circuit design in this tutorial. 
Types of finite state machines
There are many fsm(finite state machines) in existence. The two most popular used in digital combinational and sequential circuits are
 Melay Machine
 Moore Machine
Difference between melay vs moore machine
The main difference between melay and moore is the computation of the next state. In melay machine the output depends on the current state and the input variables. Where as in moore machine the output depends on the current state only. There are also other differences which are hardly highlighted any where.
Moore Machine
Moore Machine
 More number of states in moore compared to melay for same fsm.
 States changes after 1 clock cycle. Latency = 1.
 Synchronous output. Because the states are determined in a process.
 States are output.
 Less number of states in mealy compared to moore for same fsm.
 State transition on the same clock cycle. Latency = 0.
 Asynchronous output.
 Transition are output.
Melay machine fsm design in vhdl
In the below figure you can see a melay machine fsm. Fsm has four states S0, S1, S2 and S3. Outputs can be seen on the edges. Inputs are also on the edges. Transitions from one state to another take place on the bases of current state and the inputs. Fsm below is actually a counter. When input is 1 the state moves to next and when the input is 0 state jumps to previous. Counter is 4bit but only one bit is manipulated in the counter. '1' in the 4bit output moves forward or backward depending on the state and input.
The top level entity of melay machine fsm is below. Output is 4bit named count. Clock and reset are necessary signals for finite state machine. UpDw is a single bit input. When UpDw is 1 state jumps from current to next and when 0 it scroll back to previous state.
Output of the melay machine can be seen in the figure below. If you match the behavior of the simulation with the actual state machine above you will find the behavior of the two similar. Which means that the finite state machine is implemented correctly. The simulation below is run on ISim simulator by xilinx.
Melay machine fsm vhdl code
Project Code
Download the project code from the links given at the bottom of the Post.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY up_down_counter IS
PORT (Clk, Rst, UpDw: IN std_logic;
count: OUT std_logic_vector (3 DOWNTO 0));
END up_down_counter;
ARCHITECTURE mealy_beh OF up_down_counter IS
TYPE Statetype IS (S0, S1, S2, S3);
SIGNAL Currstate, Nextstate: Statetype;
BEGIN
StateReg: PROCESS (Clk, Rst)
BEGIN
IF (Rst = '1') THEN
Currstate <= S0;
ELSIF (Clk = '1' AND Clk'EVENT) THEN
Currstate <= Nextstate;
END IF;
END PROCESS;
CombLogic: PROCESS (Currstate, UpDw)
BEGIN
Nextstate <= S0;
CASE Currstate IS
WHEN S0 =>
IF (UpDw = '0') THEN
Nextstate <= S3;
count <= "0001";
ELSE
Nextstate <= S1;
count <= "0100";
END IF;
WHEN S1 =>
IF (UpDw = '0') THEN
Nextstate <= S0;
count <= "1000";
ELSE
Nextstate <= S2;
count <= "0010";
END IF;
WHEN S2 =>
IF (UpDw = '0') THEN
Nextstate <= S1;
count <= "0100";
ELSE
Nextstate <= S3;
count <= "0001";
END IF;
WHEN S3 =>
IF (UpDw = '0') THEN
Nextstate <= S2;
count <= "0010";
ELSE
Nextstate <= S0;
count <= "1000";
END IF;
END CASE;
END PROCESS;
END mealy_beh;