# Linear-feedback shift register (LFSR) design in vhdl

LFSR stands for linear feedback shift register. Although they are widely used in random electronics projects but they are quiet often neglected by the engineers community. LFSR is comprised of a series of D-flip flops, depending on the size of the LFSR. Some of the states and especially the last one is feed back to the system by going through logical XOR.

This control means every thing to hardware engineer. By knowing the states lfsr can be utilized to generate test patterns for a given circuit. lfsr can be molded to act as a counter or event generator. Ends of lfsr can be brought together to form a cascaded loop.

So a linear feed-back shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. This is a rotating register, in which one of the Flip-Flops has a XOR as its input, an XOR among two or more outputs of the remaining Flip-Flops. The outputs connected to the XOR Gate are called TAP. There are two TAPs in the below figure.

So a linear feed-back shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. This is a rotating register, in which one of the Flip-Flops has a XOR as its input, an XOR among two or more outputs of the remaining Flip-Flops. The outputs connected to the XOR Gate are called TAP. There are two TAPs in the below figure.

The initial value of the LFSR is called “seed”, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.

The circuit can be initialized with a different seed from Null vector. In the upper Figure two of the three Flip-Flops are connected to the XOR, which is a input to the other Flip-Flop. Let’s suppose that all bits are initialized to ’1’ after the reset. At each clock cycle the rotation continues and runs a sequence of pseudo random bits on the Flip Flop’s outputs, which will be repeated at a given frequency. In this case the sequence will have a length of 7 as shown in the table.

The circuit can be initialized with a different seed from Null vector. In the upper Figure two of the three Flip-Flops are connected to the XOR, which is a input to the other Flip-Flop. Let’s suppose that all bits are initialized to ’1’ after the reset. At each clock cycle the rotation continues and runs a sequence of pseudo random bits on the Flip Flop’s outputs, which will be repeated at a given frequency. In this case the sequence will have a length of 7 as shown in the table.

It can be demonstrated that the length of sequence is 2n − 1. The sequence is often associated to a polynomial where the terms different from zero are those with a position corresponding to the TAP.In this case P = 1 + x2 + x3.
Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common. |

## 8-bit lfsr in vhdl

Lets build an 8-bit lfsr in vhdl. I will design the lfsr using FSM(finite state machine). I aspect that you know what is finite state machine and how it works.

The top level entity is comprised of 2 input and 1 output ports. Input ports are clock and reset. Output port is an 8-bit number. Top level entity looks like the the one given in below figure. The picture is taken from top level RTL design in xilinx inc.

The top level entity is comprised of 2 input and 1 output ports. Input ports are clock and reset. Output port is an 8-bit number. Top level entity looks like the the one given in below figure. The picture is taken from top level RTL design in xilinx inc.

The input to lfsr is states coming back as input to XOR. The states which are taped for XOR are 0,2,3 and 4. The lfsr diagram is shown below.

Simulation result of the linear feed back register is below. On initial reset the input to system is "

**00000001**". If you now calculate manually the output by using equation Z=0(bit) XOR 2(bit) XOR 3(bit) XOR 4(bit). You will get same result as in the simulation below.### LFSR vhdl code

First the necessary vhdl libraries are included in the project. After libraries top level lfsr entity is defined in the code. In the code below top level entity name is

In architecture i first defined the two signals(

**LFSR8**. After entity input output ports declaration its time to define the internal architecture of the linear feed back register.In architecture i first defined the two signals(

**currstate**and**nextstate**) of 8-bit length. These signals are playing a vital role in lfsr working. Their purpose is to hold the current state and next state. In the process part first the reset port is defined. If reset is '1' high then current state is initialized "**00000001**". Else if its a rising edge of clock then next state is assigned to current state. Note that the reset is asynchronous and process is sensitive to input clock and reset.## Project Code

### Download the project code from the links given at the bottom of the Post.

```
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LFSR8 IS
PORT (Clk, Rst: IN std_logic;
output: OUT std_logic_vector (7 DOWNTO 0));
END LFSR8;
ARCHITECTURE LFSR8_beh OF LFSR8 IS
SIGNAL Currstate, Nextstate: std_logic_vector (7 DOWNTO 0);
SIGNAL feedback: std_logic;
BEGIN
StateReg: PROCESS (Clk,Rst)
BEGIN
IF (Rst = '1') THEN
Currstate <= (0 => '1', OTHERS =>'0');
ELSIF (Clk = '1' AND Clk'EVENT) THEN
Currstate <= Nextstate;
END IF;
END PROCESS;
feedback <= Currstate(4) XOR Currstate(3) XOR Currstate(2) XOR Currstate(0);
Nextstate <= feedback & Currstate(7 DOWNTO 1);
output <= Currstate;
END LFSR8_beh;
```

After the process block the XOR between the tap states or bits is done. The result of XOR is saved in

**feedback**signal. On the bases of the**feedback**signal**nextstate**is calculated. The statement**Nextstate <= feedback & Currstate(7 downto 1)**is concatenating the new lsb(least significant bit) which is**feedback**with the rest of the number. The**&**operator in vhdl is used for concatenation purposes. The new state is assigned to the next state. While the current state is assigned to output in the next statement.### LFSR VHDL test bench

Test bench of the project is below. The main lfsr entity is instantiated in the test bench. After instantiation it is mapped with test bench signals. Two process are defined in test bench. The first process is about clock input. Clock period is 20 ns. The second process is about resetting the system and initializing the current state with initial value.

## Project Code

### Download the project code from the links given at the bottom of the Post.

```
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Testbench IS
END Testbench;
ARCHITECTURE TBarch OF Testbench IS
COMPONENT LFSR8 IS
PORT (Clk, Rst: IN std_logic;
output: OUT std_logic_vector (7 DOWNTO 0));
END COMPONENT;
SIGNAL Clk_s, Rst_s: std_logic;
SIGNAL output_s: std_logic_vector(7 DOWNTO 0);
BEGIN
CompToTest: LFSR8 PORT MAP (Clk_s, Rst_s, output_s);
Clk_proc: PROCESS
BEGIN
Clk_s <= '1';
WAIT FOR 10 ns;
Clk_s <= '0';
WAIT FOR 10 ns;
END PROCESS clk_proc;
Vector_proc: PROCESS
BEGIN
Rst_s <= '1';
WAIT FOR 5 NS;
Rst_s <= '0';
FOR index IN 0 To 4 LOOP
WAIT UNTIL Clk_s='1' AND Clk_s'EVENT;
END LOOP;
WAIT FOR 5 NS;
ASSERT output_s = X"88" REPORT "Failed output=88";
WAIT;
END PROCESS Vector_proc;
END TBarch;
```